The Design of a Dynamic Configurable Packet Parser Based on FPGA
To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is redu...
-д хадгалсан:
| Үндсэн зохиолчид: | , |
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| Формат: | Artigo |
| Хэл сонгох: | Inglês |
| Хэвлэсэн: |
MDPI AG
2023-08-01
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| Цуврал: | Micromachines |
| Нөхцлүүд: | |
| Онлайн хандалт: | https://www.mdpi.com/2072-666X/14/8/1560 |
| Шошгууд: |
Шошго байхгүй, Энэхүү баримтыг шошголох эхний хүн болох!
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