Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits
When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of...
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| Principais autores: | , , , , , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado em: |
Wiley
2022-01-01
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| coleção: | Complexity |
| Acesso em linha: | http://dx.doi.org/10.1155/2022/8658770 |
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