Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets

A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvemen...

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Detalhes bibliográficos

Principais autores:	Kun Chen, Jingwen Yang, Tao Liu, Dawei Wang, Min Xu, Chunlei Wu, Chen Wang, Saisheng Xu, David Wei Zhang, Wenchao Liu
Formato:	Artigo
Idioma:	Inglês
Publicado em:	MDPI AG 2022-07-01
coleção:	Micromachines
Assuntos:	gate-all-around (GAA) nanosheet (NS) S/D stressor channel stress enhancement
Acesso em linha:	https://www.mdpi.com/2072-666X/13/7/1080
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