Implementation and Analysis of a 15-Level Inverter Topology With Reduced Switch Count
Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been p...
Furkejuvvon:
| Váldodahkkit: | , , , , |
|---|---|
| Materiálatiipa: | Artigo |
| Giella: | Inglês |
| Almmustuhtton: |
IEEE
2021-01-01
|
| Ráidu: | IEEE Access |
| Fáttát: | |
| Liŋkkat: | https://ieeexplore.ieee.org/document/9373402/ |
| Fáddágilkorat: |
Eai fáddágilkorat, Lasit vuosttaš fáddágilkora!
|