Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets
High Level Synthesis (HLS) tools targeting Field Programmable Gate Arrays (FPGAs) aim to provide a method for programming these devices via high-level abstractions. Initially, HLS support for FPGAs focused on compiling C/C++ to hardware circuits. This raised the issue of determining the programming...
Uloženo v:
| Hlavní autoři: | , , |
|---|---|
| Médium: | Artigo |
| Jazyk: | Inglês |
| Vydáno: |
IEEE
2020-01-01
|
| Edice: | IEEE Access |
| Témata: | |
| On-line přístup: | https://ieeexplore.ieee.org/document/9170625/ |
| Tagy: |
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
|