Testable binary adder circuit based on a 16‑bit section group
A testable functional‑logical circuit of a binary adder based on a 16‑bit group of 4‑bit sections is considered. The design provides simultaneous carry propagation within each section and section group, and sequential carry propagation between groups. The circuit was developed within the concept of...
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| Hoofdauteur: | |
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| Formaat: | Artigo |
| Taal: | Inglês |
| Gepubliceerd in: |
Politekhperiodika
2003-02-01
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| Reeks: | Технологія та конструювання в електронній апаратурі |
| Onderwerpen: | |
| Online toegang: | https://tkea.com.ua/index.php/journal/article/view/1303 |
| Tags: |
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