A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting
Increasing the size of target arrays is beneficial to reuse fault-free processing elements (PEs) for reconfiguring 2-D mesh-connected processor arrays with faults. In this paper, we discuss the reconfiguration problem under the row and column rerouting constraint. We present a novel approach, making...
Furkejuvvon:
| Váldodahkkit: | , , , , |
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| Materiálatiipa: | Artigo |
| Giella: | Inglês |
| Almmustuhtton: |
IEEE
2017-01-01
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| Ráidu: | IEEE Access |
| Fáttát: | |
| Liŋkkat: | https://ieeexplore.ieee.org/document/8076838/ |
| Fáddágilkorat: |
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