A 2.1 GS/s 2-Channel Pipeline-SAR ADC With Speed-Enhanced Bootstrap Switch and Low-Latency SAR Logic

This paper introduces a 12-bit 2-channel interleaved Pipelined Successive Approximation Register (Pipelined-SAR) Analog-to-Digital Converter (ADC) capable of operating at 2.1 GS/s. A speed-enhanced bootstrap switch that enhances the sampling speed is featured so that the overall speed bottleneck of...

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Hlavní autoři:	Tao Fu, Xianshan Wen, Liang Fang, Ping Gui
Médium:	Artigo
Jazyk:	Inglês
Vydáno:	IEEE 2025-01-01
Edice:	IEEE Access
Témata:	Analog-to-digital converter (ADC) pipelined SAR ADC successive approximation register (SAR) SAR logic bootstrap switch
On-line přístup:	https://ieeexplore.ieee.org/document/10928983/
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