Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Floating-point division is indispensable and becoming increasingly important in many modern applications. To improve speed performance of floating-point division in actual microprocessors, this paper proposes a low-latency architecture with a multi-precision architecture for floating-point division...

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Auteurs principaux:	Jincheng Xia, Wenjia Fu, Ming Liu, Mingjiang Wang
Format:	Artigo
Langue:	Inglês
Publié:	MDPI AG 2021-05-01
Collection:	Applied Sciences
Sujets:	arithmetic floating-point division low latency hardware configurable architecture
Accès en ligne:	https://www.mdpi.com/2076-3417/11/11/4988
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