Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit
This article proposed the use of an efficient ternary multiplexer as a building block in the implementation of ternary adders and multipliers. These designs aim to reduce the power consumption and minimize the transistor counts while maintaining low noise sensitivity. All ternary circuits use carbon...
Guardat en:
| Autors principals: | , |
|---|---|
| Format: | Artigo |
| Idioma: | Inglês |
| Publicat: |
Elsevier
2025-03-01
|
| Col·lecció: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| Matèries: | |
| Accés en línia: | http://www.sciencedirect.com/science/article/pii/S2772671125000191 |
| Etiquetes: |
Sense etiquetes, Sigues el primer a etiquetar aquest registre!
|