CAMPuS: Concurrent Acceleration of Memory Access and Parallel Processing in Near-Memory SpMV Architecture
Sparse matrix-vector multiplication (SpMV) is one of the key computations in many deep-learning networks. However, the performance to compute SpMV is often limited by the DRAM bandwidth. To resolve such DRAM bandwidth issues, several studies have proposed DIMM-based near-memory processing (NMP) arch...
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| Hauptverfasser: | , |
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| Format: | Artigo |
| Sprache: | Inglês |
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IEEE
2024-01-01
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| Schriftenreihe: | IEEE Access |
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| Online-Zugang: | https://ieeexplore.ieee.org/document/10807171/ |
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