Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor
Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with...
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| Glavni autori: | , |
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| Format: | Artigo |
| Jezik: | Inglês |
| Izdano: |
MDPI AG
2021-06-01
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| Serija: | Algorithms |
| Teme: | |
| Online pristup: | https://www.mdpi.com/1999-4893/14/7/198 |
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