DDX-JK: a data-driven and explainable machine learning framework for reducing circuit simulation overhead in CMOS JK flip-flop designs

Abstract Introduction Transistor count is a critical circuit-level metric, as it directly influences power consumption, propagation delay, leakage, and overall design complexity in VLSI systems. In Electronic Design Automation (EDA) workflows, variations in transistor count significantly affect simu...

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Principais autores:	Arjun Sunil Rao, R. Roopalakshmi, Samrat Sharma, Samana Nagendran, Prachita Singal, Aditi Javeri, Nandana Kamath, Adithya Sriraman
Format:	Artigo
Jezik:	Inglês
Izdano:	Springer 2026-05-01
Serija:	Discover Applied Sciences
Teme:	VLSI CMOS circuits JK flip-flops Electronic design automation Machine learning-based prediction Explainable AI
Online dostop:	https://doi.org/10.1007/s42452-026-08770-3
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