A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor

Computer designers have included techniques such as speculative execution and caching to optimize speed and performance. Unfortunately, they could be exploited by the recently discovered cache-side channel attack, spectre. The purpose of this research is to resolve this problem on the open-source RI...

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Autors principals:	Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
Format:	Artigo
Idioma:	Inglês
Publicat:	IEEE 2021-01-01
Col·lecció:	IEEE Access
Matèries:	RISC-V spectre side-channel attack machine learning cache memory hardware performance counters
Accés en línia:	https://ieeexplore.ieee.org/document/9645559/
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