A PERFORMANCE ANALYSIS OF CLASSIFIED BINARY ADDER ARCHITECTURES AND THE VHDL SIMULATIONS
In this paper, the four binary adder architectures belong to a different adder class are studied and compared with each other to analyse their performances. Comparisons include the unit-gate models for area and delay. As the performance measure, the product of the area and the delay is used. By a VH...
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| Hlavní autoři: | , |
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| Médium: | Artigo |
| Jazyk: | Inglês |
| Vydáno: |
İstanbul University-Cerrahpasa
2003-12-01
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| Edice: | Electrica |
| Témata: | |
| On-line přístup: | https://www.electricajournal.org/index.php/pub/article/view/181 |
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