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Designing reliable and efficient networks on chips
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...
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| Autor principal: | |
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| Formato: | Livro |
| Idioma: | Inglês |
| Publicado em: |
Springer Netherlands :,
2009
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| Edição: | 1st ed. 2009. |
| Assuntos: | |
| Acesso em linha: | https://minerva.ufrj.br/F/?func=direct&doc_number=000920199&local_base=UFR01 |
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