Design of a JFET and radiation PIN detector integrated on a high resistivity silicon substrate using a high temperature process - A.T. Medel de Gante (Revista Mexicana de Física, 2006)
In this work, a fabrication process with a PIN diode integrated in a high resistivity silicon wafer is presented. This process uses high temperature thermal treatments to improve the JFET characteristics. Using simulation programs and statistical tools, the contribution of diverse process steps on the characteristics of the JFET manufactured in the same wafer with a PIN diode are evaluated. The use of thermal treatments has a significant impact on the JFET characteristics. The proposed JFET design offers an improved solution for the integration of JFETs on high resitivity silicon wafers.