Marshall, J. C., & Vernier, P. T. (2007). Electro-Physical Technique for Post-Fabrication Measurements of CMOS Process Layer Thicknesses. J Res Natl Inst Stand Technol.
Citação norma ChicagoMarshall, Janet C., and P. Thomas Vernier. "Electro-Physical Technique for Post-Fabrication Measurements of CMOS Process Layer Thicknesses." J Res Natl Inst Stand Technol 2007.
MLA CitationMarshall, Janet C., and P. Thomas Vernier. "Electro-Physical Technique for Post-Fabrication Measurements of CMOS Process Layer Thicknesses." J Res Natl Inst Stand Technol 2007.
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