Cheng, Y., Chen, H., Su, J., Shao, C., Wang, C., Chang, C., & Wu, Y. (2014). Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure. Nanoscale Res Lett.
Styl ChicagoCheng, Ya-Chi, Hung-Bin Chen, Jun-Ji Su, Chi-Shen Shao, Cheng-Ping Wang, Chun-Yen Chang, a Yung-Chun Wu. "Characterizing the Electrical Properties of Raised S/D Junctionless Thin-film Transistors With a Dual-gate Structure." Nanoscale Res Lett 2014.
Citace podle MLACheng, Ya-Chi, et al. "Characterizing the Electrical Properties of Raised S/D Junctionless Thin-film Transistors With a Dual-gate Structure." Nanoscale Res Lett 2014.
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