A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote

Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability...

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Main Authors: Abhishek Das, Nur A. Touba
Format: Artigo
Sprog:Inglês
Udgivet: MDPI AG 2020-04-01
Serier:Electronics
Fag:
error correcting codes
single error correction
orthogonal Latin square codes
Hamming codes
shared majority vote
cache
Online adgang:https://www.mdpi.com/2079-9292/9/5/709
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