VLSI-SOC: from systems to chips IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany - IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration (IFIP Advances in Information and Communication Technology, 2006)
International Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springeronline.com. For more information about IFIP, please visit www.ifip.org. Effect of power optimizations on soft error rate -- Dynamic models for substrate coupling in mixed-mode systems -- Hinoc: a hierarchical generic approach for on-chip communication, testing and debugging of SoCs -- Automated conversion of systemC fixed-point data types -- Exploration of sequential depth by evolutionary algorithms -- Validation of asynchronous circuit specifications using IF/CADP -- On-chip property verification using assertion processors -- Run-time FPGA reconfiguration for power-/cost-optimized real-time systems -- A switched opamp based 10 bits integrated ADC for ultra low power applications -- Exploring the capabilities of reconfigurable hardware for OFDM-based wlans -- Software-based test for nonprogrammable cores in bus-based system-on-chip architectures -- Optimizing SOC test resources using dual sequences -- A novel full automatic layout generation strategy for static CMOS circuits -- Low power java processor for embedded applications -- Impact of gate leakage on efficiency of circuit block switch-off schemes -- Evaluation methodology for single electron encoded threshold logic gates -- Asynchronous integration of coarse-grained reconfigurable XPP-arrays into pipelined risc processor datapath -- Gray encoded arithmetic operators applied to FFT and FIR dedicated datapaths -- Stuck-at-fault testability of SPP three-level logic forms.